Original Article

Metrology of silicon wafers under thermal and mechanical stress

¹ Institute of Innovation and Circular Economy, Asia University, Taichung, Taiwan
² Department of Medical Research, China Medical University Hospital, China Medical University, Taichung, Taiwan
³ Mechatronic Engineering Technological University Dublin, Dublin 15, Ireland

^* e-mail: nima.gorji@tudublin.ie

Received: 3 December 2024
Accepted: 20 May 2025

Abstract

In this study, we deploy a methodology to map the surface displacement (vertical displacement) in the Z direction that is often induced in silicon dies inside packaged chips. This metrology study will focus on the impact of thermal and mechanical (thermo-mechanical) stresses on the surface flatness of a single-chip ball grid array (BGA) chip. We developed a new formulation to map the surface displacement of the die in 3 dimensions for the chips that were stressed at different temperatures [30 °C, 50 °C, 100 °C, 150 °C] and for three different pressures applied to the package [10 MPa, 30 MPa, 60 MPa, 80 MPa]. These thermo-mechanical stresses are often applied to the die during the encapsulation process. The simulation results are similar to the trend of change in vertical displacement maps measured by optical interferometry in literature. The modeling and simulation results show that the flatness of the silicon die surface changes to a concave or convex shape by increasing the thermo-mechanical stress, which results in malfunction of the chip and reduces the chips’ operational reliability.